Systems on chip (System On Chip, SoC), such as a single-core operating system (Operating System, OS) with multiple processes, a symmetric multiprocessing (Symmetric Multiprocessing, SMP) system, and an asymmetric multiprocessing (Asymmetric Multiprocessing, AMP) system, all relate to access to a shared resource.
For the single-core OS system, resource synchronization and sharing are generally implemented by a semaphore provided by the operating system. The semaphore may be implemented by software without support of hardware. In the single-core OS system, when the multiple processes access a shared resource, a semaphore needs to be acquired first. The semaphore is generally implemented by a data structure (that is, in a software data structure manner) provided by the operating system. The processes obtain execution time of a processor according to a time slice. Therefore, access of the processor to the semaphore is unique at any time, and a problem of bus contention does not occur.
In a multiprocessing system, execution by each processor is completely independent. Therefore, each processor may perform an operation of independent access to a resource at any time. In this case, bus contention exists. A problem of bus contention in semaphore access cannot be solved in a software manner. Therefore, resource synchronization and sharing need support of hardware. For example, an ARM is generally implemented by an exclusive operation of an AMBA bus. Two conditions need to be met for implementing resource synchronization and sharing in the multiprocessing system: support of hardware and that a processor is capable of initiating a synchronization operation.
However, when the multiprocessing system accesses a shared resource, a bus needs to support a synchronization operation and a processor needs to support a synchronous access operation, which not only increases difficulty of logic, but also imposes a limitation on selection of the processor and reduces flexibility.
In a practical SoC design, it is often encountered that conditions for resource synchronization and sharing fail to be met. If there is a control processor, such as ARM7, Cortex M3, and MCU, in a system, the processor is used for system control or low power consumption control, and the control processor cannot initiate a synchronization operation. In addition, the control processor and a main processor may access a same resource. In this case, a resource synchronization problem exists. This type of processor is generally not mounted on a same bus as the main processor. Therefore, it is difficult to implement resource synchronization and sharing by using unified bus support.